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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. TPSM84209 slvse31 ? january 2018 TPSM84209 4.5-v to 28-v input, 1.2-v to 6-v output, 2.5-a power module 1 1 features 1 ? complete integrated power solution allows small footprint, low-profile design ? 4.5-mm 4-mm 2-mm qfn package ? wide-output voltage range (1.2 v to 6 v) ? fixed switching frequency (750 khz) ? advanced eco-mode ? for light load efficiency ? programmable undervoltage lockout (uvlo) ? overtemperature thermal shutdown protection ? overcurrent protection (hiccup mode) ? safe pre-bias output start-up ? operating ic junction range: ? 40 c to +125 c ? operating ambient range: ? 40 c to +85 c ? enhanced thermal performance: 29.5 c/w ? meets en55011 radiated emi standards ? integrated shielded inductor ? create a custom design using the TPSM84209 with the webench ? power designer 2 applications ? industrial and motor controls ? automated test equipment ? medical and imaging equipment ? high-density power systems 3 description the TPSM84209 power module is an easy-to-use integrated power supply that combines a 2.5-a dc- dc converter with a shielded inductor and passives into a low-profile qfn package. this total power solution allows as few as four external components while maintaining an ability to adjust key parameters to meet specific design requirements. the wide input voltage range and small package size of the TPSM84209 makes the device an excellent fit for power rails that require up to 2.5 a of output current. the qfn package is easy to solder to a printed circuit board and has excellent power dissipation capability. the TPSM84209 offers flexibility with many features and is ideal for powering a wide range of devices and systems. device information (1) device number package body size TPSM84209 b3qfn (43) 4.50 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space space space space space simplified application efficiency vs output current vin gnd v in vout r fbb v out fb r fbt c in c out en TPSM84209 copyright ? 2018, texas instruments incorporated output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 40 50 60 70 80 90 100 eff1 v out = 5.0 v v in = 12 v v in = 24 v advance information technical documents support &community ordernow productfolder tools & software
2 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics (v in = 5 v) ............................ 7 6.7 typical characteristics (v in = 12 v) .......................... 8 6.8 typical characteristics (v in = 24 v) .......................... 9 7 detailed description ............................................ 10 7.1 overview ................................................................. 10 7.2 functional block diagram ....................................... 10 7.3 feature description ................................................. 11 7.4 device functional modes ........................................ 19 8 applications and implementation ...................... 20 8.1 application information ............................................ 20 8.2 typical application .................................................. 20 9 power supply recommendations ...................... 21 10 layout ................................................................... 22 10.1 layout guidelines ................................................. 22 10.2 layout examples ................................................... 22 11 device and documentation support ................. 23 11.1 device support .................................................... 23 11.2 receiving notification of documentation updates 23 11.3 community resources .......................................... 23 11.4 trademarks ........................................................... 23 11.5 electrostatic discharge caution ............................ 23 11.6 glossary ................................................................ 23 12 mechanical, packaging, and orderable information ........................................................... 23 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes january 2018 * initial release advance information
3 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) g = ground, i = input, o = output 5 pin configuration and functions rvq package 43-pin b3qfn top view pin functions pin type (1) description name no. dnc 6, 7 ? do not connect. do not connect these pins to gnd or to any other voltage. these pins are connected to internal circuitry. each pin must be soldered to an isolated pad. en 9 i enable pin. an open drain/collector device can be used to control the en function. the module is disabled when this pin is pulled low. this pin can also be connected to an external resistor divider connected between vin and gnd to adjust the uvlo above the internal default setting. float this pin when not used. fb 1 i feedback input. to adjust the output voltage connect this pin to the center point of an external resistor divider connected between vout and gnd. gnd 8 g ground pin. this is the return current path for the device. connect this pin to the input source return, the load return, and to the ground side of the vin and vout bypass capacitors using power ground planes on the pcb. sw 4, 5 o switch node. these pins are connected to the input side of the internal output inductor. do not place any external components on these pins or tie them to a pin of another function. vin 2 i input voltage. connect this pin to the input source and connect external bypass capacitors between this pin and gnd, close to the module. vout 3 o output voltage. this pin is connected to the internal output inductor. connect this pin to the output load and connect external bypass capacitors between this pin and gnd close to the module. advance information fb vin vout 1 2 3 6 5 dnc sw sw 7 8 9 4 dnc gnd en
4 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under the recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the ambient temperature is the air temperature of the surrounding environment. the junction temperature is the temperature of the internal power ic when the deviceis powered. operating below the maximum ambient temperature, as shown in the safe operating area (soa) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the module is never exceeded. 6 specifications 6.1 absolute maximum ratings over operating ambient temperature range (unless otherwise noted) (1) min max unit input voltage vin ? 0.3 30 v en, fb ? 0.3 7 v output voltage sw ? 0.3 30 v vout ? 0.3 7 v mechanical shock mil-std-883d, method 2002.3, 1 msec, 1/2 sine, mounted tbd g mechanical vibration mil-std-883d, method 2007.2, 20 to 2000 hz tbd g operating ic junction temperature, t j (2) ? 40 125 c operating ambient temperature, t a (2) ? 40 85 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) tbd v charged-device model (cdm), per jedec specification jesd22- c101 (2) 1000 (1) the minimum recommended input voltage is 4.5 v or (v out 1.3), whichever is greater. 6.3 recommended operating conditions over operating ambient temperature range (unless otherwise noted) min max unit input voltage, v in 4.5 (1) 28 v output voltage, v out 1.2 6 v en voltage, v en 0 6 v output current, i out 0 2.5 a operating ambient temperature, t a ? 40 85 c operating ic junction temperature, t j ? 40 125 advance information
5 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance, r ja , applies to devices soldered directly to a 63 mm 50 mm, 4-layer pcb with 2 oz. copper and natural convection cooling. additional airflow reduces r ja . (3) the junction-to-top characterization parameter, jt , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51-2a (section 6 and 7). t j = jt pdis + t t ; where pdis is the power dissipated in the device and t t is the temperature of the top of the device. (4) the junction-to-board characterization parameter, jb , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51-2a (sections 6 and 7). t j = jb pdis + t b ; where pdis is the power dissipated in the device and t b is the temperature of the board 1mm from the device. 6.4 thermal information thermal metric (1) TPSM84209 unit rkh (qfn) 9 pins r ja junction-to-ambient thermal resistance (2) 32.7 c/w jt junction-to-top characterization parameter (3) 2.2 c/w jb junction-to-board characterization parameter (4) 17 c/w (1) the minimum recommended input voltage is 4.5 v or (v out 1.3), whichever is greater. (2) the overall output voltage tolerance will be affected by the tolerance of the external r fbt and r fbb resistors. 6.5 electrical characteristics over ? 40 c to +85 c ambient temperature, v in = 12 v, v out = 3.3 v, i out = 2.5 a, (unless otherwise noted); c in1 = 10 f, 50 v, 1210 ceramic; c in2 = 100- f, 35-v, electrolytic; c out = 2 47- f, 16-v, 1210 ceramic. minimum and maximum limits are specified through production test or by design. typical values represent the most likely parametric norm and are provided for reference only. parameter test conditions min typ max unit input voltage (v in ) v in input voltage over i out range 4.5 (1) 28 v uvlo v in undervoltage lockout v in increasing 3.8 4.1 4.4 v v in decreasing 3.3 3.6 3.9 v i shdn shutdown supply current v en = 0 v 2 a output voltage (v out ) v out(adj) output voltage adjust over i out range 1.2 6 v v out(ripple) output voltage ripple 20-mhz bandwidth 22 mv feedback v fb feedback voltage (2) t a = 25 c, i out = 0 a 0.581 0.596 0.611 v temperature variation ? 40 c t j 125 c, i out = 0 a 0% 2.5% line regulation t a = 25 c, 8 v v in 28 v, i out = 0 a 6 mv load regulation over i out range, t a = 25 c 12 mv current i out output current natural convection, t a = 25 c 0 2.5 a overcurrent threshold 4.8 a performance ? efficiency v in = 24 v, i out = 1 a v out = 5 v 86.5% v out = 3.3 v 82.7% v out = 2.5 v 79.3% v in = 12 v, i out = 1 a v out = 5 v 91.7% v out = 3.3 v 89.0% v out = 2.5 v 86.8% transient response 25% to 75% load step 1 a/ s slew rate over/undershoot 90 mv recovery time 100 s soft start t ss internal soft-start time 5 ms advance information
6 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over ? 40 c to +85 c ambient temperature, v in = 12 v, v out = 3.3 v, i out = 2.5 a, (unless otherwise noted); c in1 = 10 f, 50 v, 1210 ceramic; c in2 = 100- f, 35-v, electrolytic; c out = 2 47- f, 16-v, 1210 ceramic. minimum and maximum limits are specified through production test or by design. typical values represent the most likely parametric norm and are provided for reference only. parameter test conditions min typ max unit (3) a minimum of 10 f ceramic input capacitance is required for proper operation. an additional 47 f of bulk capacitance is recommended for applications with transient load requirements. (4) a minimum of 94 f (or 2 47 f) of ceramic output capacitance is required. locate the capacitance close to the device. adding additional ceramic or non-ceramic capacitance close to the load improves the response of the regulator to load transients. (5) the maximum output capacitance of 500 f can be made up of all ceramic type or a combination of both ceramic and non-ceramic type. switching frequency f sw switching frequency 578 750 923 khz enable (en) v en-rising en threshold rising 1.21 1.28 v v en-fallin falling 1.1 1.19 v i en en input current v en = 1 v 0.7 a en hysteresis current v en = 1.5 v 1.55 a thermal t shdn thermal shutdown shutdown temperature 165 c hysteresis 10 c capacitance c in external input capacitance ceramic type 10 (3) f non-ceramic type 47 (3) f c out external output capacitance ceramic type 94 (4) 500 (5) f non-ceramic type 500 (5) f advance information
7 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 typical characteristics (v in = 5 v) t a = 25 c, unless otherwise noted. figure 1. efficiency vs output current figure 2. power dissipation vs output current c out = 2 47 f ceramic figure 3. voltage ripple vs output current v out = 2.5 v figure 4. safe operating area v out = 3.3 v figure 5. safe operating area output current (a) power dissipation (w) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.3 0.6 0.9 1.2 1.5 1.8 d002 v out 3.3 v 2.5 v 1.8 v 1.2 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d004 airflow 100lfm nat conv output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 40 50 60 70 80 90 100 d001 v out 3.3 v 2.5 v 1.8 v 1.2 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d005 airflow 100lfm nat conv advance information output current (a) output voltage ripple (mv) 0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60 70 80 90 d003 v out 1.2 v 1.8 v 2.5 v 3.3 v
8 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 typical characteristics (v in = 12 v) t a = 25 c, unless otherwise noted. figure 6. efficiency vs output current figure 7. power dissipation vs output current c out = 2 47 f ceramic figure 8. voltage ripple vs output current v out = 2.5 v figure 9. safe operating area v out = 3.3 v figure 10. safe operating area v out = 5 v figure 11. safe operating area output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d010 airflow 100lfm nat conv advance information output current (a) power dissipation (w) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.3 0.6 0.9 1.2 1.5 1.8 d007 v out 5.0 v 3.3 v 2.5 v 1.8 v output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 40 50 60 70 80 90 100 d006 v out 5.0 v 3.3 v 2.5 v 1.8 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d009 airflow 100lfm nat conv output current (a) output voltage ripple (mv) 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 180 d008 v out 1.8 v 2.5 v 3.3 v 5.0 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d011 airflow 200lfm 100lfm nat conv
9 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics (v in = 24 v) t a = 25 c, unless otherwise noted. figure 12. efficiency vs output current figure 13. power dissipation vs output current c out = 2 47 f ceramic figure 14. voltage ripple vs output current v out = 3.3 v figure 15. safe operating area v out = 5 v figure 16. safe operating area advance information output current (a) output voltage ripple (mv) 0.0 0.5 1.0 1.5 2.0 2.5 0 20 40 60 80 100 120 140 160 180 d014 v out 2.5 v 3.3 v 5.0 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d016 airflow 400lfm 200lfm 100lfm nat conv output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 40 50 60 70 80 90 100 d012 v out 5.0 v 3.3 v 2.5 v output current (a) ambient temperature (c) 0.0 0.5 1.0 1.5 2.0 2.5 25 35 45 55 65 75 85 95 d015 airflow 200lfm 100lfm nat conv output current (a) power dissipation (w) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.3 0.6 0.9 1.2 1.5 1.8 d013 v out 5.0 v 3.3 v 2.5 v
10 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the TPSM84209 is a highly integrated 28-v input, 2.5-a, synchronous step-down power module with pwm, mosfets, inductor, and control circuitry integrated into a low-profile, overmolded, qfn package. this device enables small designs by integrating all but the input and output capacitors and voltage-setting resistor divider while keeping the ability to adjust key parameters to meet specific design requirements. the TPSM84209 operates at a 750-khz fixed switching frequency and features advanced eco-mode ? pulse-skip operation for improved light-load efficiency. the TPSM84209 provides an adjustable output-voltage range of 1.2 v to 6 v using a simple external-resistor divider. the TPSM84209 provides accurate voltage regulation for a variety of loads by using an internal voltage reference that is 2.5% accurate over temperature. the output-voltage rise time is controlled by a fixed 5-ms soft start. input uvlo is internally set at 4.1 v, but can be adjusted upward using a resistor divider on the en pin of the module. the en pin can also be pulled low to put the module in standby mode to reduce input quiescent current. thermal shutdown and current limit features protect the device during an overload condition. a 9-pin, 4-mm 4.5-mm b3qfn package that includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications. 7.2 functional block diagram vin gnd vout + + vref comp power stage and control logic thermal shutdown shutdown logic ocp vin uvlo oscillator soft start fb en sw copyright ? 2018, texas instruments incorporated advance information
11 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 adjusting the output voltage a resistor divider connected to the fb pin (pin 1) programs the output voltage of the TPSM84209. the output voltage adjustment range is from 1.2 v to 6 v. figure 17 shows the feedback resistor connection for setting the output voltage. the recommended value of r fbt is 10 k . depending on the output voltage, a feed-forward capacitor, c ff , may be required for optimum performance. table 1 lists the closest standard e96 value for the r fbb resistor and the recommended c ff value for a number of common output voltages. for other output voltages, the value of the required r ffb resistor can be calculated using equation 1 . (1) figure 17. setting the output voltage table 1. standard r fbb resistor values v out (v) r fbb (k ? ) c ff (pf) v out (v) r fbb (k ? ) c ff (pf) 1.2 10.0 330 3.7 1.96 open 1.3 8.45 330 3.8 1.87 open 1.4 7.50 330 3.9 1.82 open 1.5 6.65 330 4.0 1.74 open 1.6 6.04 330 4.1 1.69 open 1.7 5.36 330 4.2 1.65 open 1.8 4.99 330 4.3 1.62 open 1.9 4.64 330 4.4 1.58 open 2.0 4.22 330 4.5 1.54 open 2.1 4.02 330 4.6 1.50 open 2.2 3.74 330 4.7 1.47 open 2.3 3.48 330 4.8 1.43 open 2.4 3.32 330 4.9 1.40 open 2.5 3.16 open 5.0 1.37 open 2.6 3.01 open 5.1 1.33 open 2.7 2.87 open 5.2 1.30 open 2.8 2.74 open 5.3 1.27 open 2.9 2.61 open 5.4 1.24 open 3.0 2.49 open 5.5 1.22 open 3.1 2.37 open 5.6 1.20 open 3.2 2.32 open 5.7 1.18 open 3.3 2.21 open 5.8 1.15 open 3.4 2.15 open 5.9 1.13 open 3.5 2.05 open 6.0 1.10 open 3.6 2.00 open vout fb r fbt 10 k r fbb c ff gnd 6 r fbb = (k ) (v out 0.6) advance information
12 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.2 operating range the TPSM84209 operates over a wide input voltage and output voltage range; however, not all output voltages can operate over the entire input voltage range. the maximum and minimum input voltage limits are shown in figure 18 . the TPSM84209 can be operated between the maximum and minimum v in limit lines. operating above the maximum v in line may cause the device to skip pulses in order to maintain the regulated output voltage. figure 18. input voltage vs output voltage 7.3.3 output current rating the maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and ambient temperature. the TPSM84209 is capable of delivering up to 2.5 a of output current; however refer to figure 19 and figure 20 for maximum current ratings based on operating conditions of the specific application. figure 19. output current derating t a = 25 c figure 20. output current derating t a = 85 c output current (a) input voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 d018 v out 6 v 5 v 3.3 v 2.5 v 1.8 v 1.2 v output current (a) input voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 d019 v out 6 v 5 v 3.3 v 2.5 v 1.8 v 1.2 v output voltage (v) input voltage (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 4 8 12 16 20 24 28 32 d017 maximum v in minimum v in advance information
13 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.4 output capacitor selection the TPSM84209 requires a minimum of two 47 f ceramic output capacitors. the effects of temperature and capacitor voltage rating must be considered when selecting capacitors to meet the minimum required capacitance. the required output capacitance must be comprised of all ceramic capacitors or a combination of ceramic and bulk capacitors. when adding additional output capacitance, ceramic capacitors or a combination of ceramic and bulk capacitors can be used. the required capacitance above the minimum is determined by actual transient deviation requirements. see table 2 for a preferred list of output capacitors by vendor. (1) capacitor supplier verification, rohs, lead-free and material details consult capacitor suppliers regarding availability, material composition, rohs and lead-free status, and manufacturing process requirements for any capacitors identified in this table. (2) specified capacitance values. (3) maximum esr at 100 khz, 25 c. table 2. recommended output capacitors (1) vendor series part number capacitor characteristics working voltage (v) capacitance (2) ( f) esr (3) (m ? ) tdk x5r c3225x5r1c106k 16 10 2 murata x5r grm32er61c106k 16 10 2 tdk x5r c3225x5r1c226m 16 22 2 murata x5r grm32er61c226k 16 22 2 tdk x5r c3225x5r1a476m 10 47 2 murata x5r grm32er61c476k 16 47 3 tdk x5r c3225x5r0j107m 6.3 100 2 murata x5r grm32er60j107m 6.3 100 2 murata x5r grm32er61a107m 10 100 2 kemet x5r c1210c107m4pac7800 16 100 2 panasonic poscap 6tpe100mi 6.3 100 18 panasonic poscap 6tpf220m9l 6.3 220 9 panasonic poscap 6tpe220ml 6.3 220 12 7.3.5 feed-forward capacitor, c ff the TPSM84209 is internally compensated to be stable over the operating frequency and output voltage range. however, depending on the output voltage, an additional feed-forward capacitor, c ff , may be required for optimum performance. if required, the external feed-forward capacitor must be placed in parallel with the top resistor divider, r fbt . the placement of c ff is shown in figure 17 . table 1 lists the recommended c ff value for each output voltage shown. from the table, output voltages 2.5 v and greater do not require a c ff capacitor. advance information
14 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) capacitor supplier verification, rohs, lead-free and material details consult capacitor suppliers regarding availability, material composition, rohs and lead-free status, and manufacturing process requirements for any capacitors identified in this table. (2) specified capacitance values (3) maximum esr at 100 khz, 25 c. 7.3.6 input capacitor selection the TPSM84209 requires a ceramic input capacitor with a minimum effective capacitance of 10 f. use only high-quality ceramic type x5r or x7r capacitors with sufficient voltage rating. an additional 47 f of non- ceramic capacitance is recommended for applications with transient load requirements. the voltage rating of input capacitors must be greater than the maximum input voltage. to compensate for the derating of ceramic capacitors, ti recommends a voltage rating of twice the maximum input voltage. at worst case, when operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 1.25 arms. table 3 includes a preferred list of capacitors by vendor. table 3. recommended input capacitors (1) vendor series part number capacitor characteristics working voltage (v) capacitance (2) ( f) esr (3) (m ? ) tdk x5r c3225x5r1h106k 50 10 3 murata x7r grm32er71h106k 50 10 2 murata x7r grm32er71j106k 63 10 2 panasonic za eehza1h101p 50 100 28 panasonic za eehza1j560p 63 56 30 7.3.7 undervoltage lockout (uvlo) the TPSM84209 device has an internal uvlo circuit which prevents the device from operating until the v in voltage exceeds the uvlo rising threshold, (4.1 v (typical)). the device is disabled when the vin pin voltage falls below the internal v in uvlo threshold. the internal v in uvlo threshold has a hysteresis of 500 mv. applications may require a higher uvlo threshold to prevent early turnon, for sequencing requirements or to prevent input current draw at lower input voltages. an external resistor divider can be added to the en pin to adjust the uvlo threshold higher. the external resistor divider can be configured as shown in figure 21 . table 4 lists standard values for r uvlo1 and r uvlo2 to adjust the uvlo voltage higher. figure 21. adjustable uvlo table 4. standard resistor values for adjusting uvlo v in uvlo (v) 4.5 10 15 18 20 r uvlo1 (k ) 68.1 68.1 68.1 68.1 68.1 r uvlo2 (k ) 25.5 9.53 6.04 4.99 4.42 advance information en gnd r uvlo1 r uvlo2 vin
15 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.8 enable (en) the en pin provides electrical on and off control of the device. when the en pin voltage exceeds the threshold voltage, the device begins operation. if the en pin voltage is pulled below the threshold voltage, the regulator stops switching and enters the low-quiescent current state. the en pin has an internal pullup-current source, which allows the user to float the en pin to enable the device. if an application requires control of the en pin, use open-drain or open-collector output logic to interface with the pin. figure 22 shows the typical application of the enable function. turning q1 on applies a low voltage to the enable control pin and disables the output of the supply, shown in figure 23 . if q1 is turned off, the supply executes a soft-start power-up sequence, as shown in figure 24 . figure 22. typical enable control figure 23. enable turnoff figure 24. enable turnon 7.3.9 internal soft start the TPSM84209 device uses the internal soft-start function. the internal soft-start time is set to 5 ms typically. 7.3.10 safe start-up into pre-biased outputs the device has been designed to prevent the low-side mosfet from discharging a pre-biased output. during monotonic pre-biased start-up, both high-side and low-side mosfets are not allowed to be turned on until the internal soft-start voltage is higher than fb pin voltage. advance information en gnd q1 en control
16 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.11 light load efficiency / eco-mode the device is designed to operate in high-efficiency, pulse-skipping mode under light load conditions. as the load current on the output is decreased, a point is reached where the energy delivered by a single switching pulse is more than the load can absorb. this causes the output voltage to rise slightly. this rise in output voltage is sensed by the feedback loop, and the device responds by skipping one or more switching cycles until the output voltages falls back to the setpoint. at very light loads or no load, many switching cycles are skipped. the observed effect during this pulse-skipping mode of operation is an increase in the peak-to-peak ripple voltage and a decrease in the ripple frequency. the load current where pulse skipping begins is a function of the input voltage and output voltage. figure 25 is a plot of the pulse-skipping threshold current as a function of input voltage for a number of popular output voltages. figure 25. pulse-skipping threshold input voltage (v) output current (a) 4 8 12 16 20 24 28 0.0 0.5 1.0 1.5 2.0 2.5 pskp v out 1.2 v 1.8 v 2.5 v 3.3 v 5 v advance information
17 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.12 overcurrent protection for protection against load faults, the TPSM84209 incorporates output overcurrent protection. applying a load that exceeds the overcurrent threshold of the regulator causes the output to shut down. following shutdown, the module periodically attempts to recover by initiating a soft-start power-up as shown in figure 26 . this is described as a hiccup mode of operation, where the module continues in a cycle of successive shutdown and power up until the load fault is removed. during this period, the average current flowing into the fault is significantly reduced which reduces power dissipation. once the fault is removed, the module automatically recovers and returns to normal operation as shown in figure 27 . figure 26. overcurrent limiting figure 27. removal of overcurrent 7.3.13 output overvoltage protection (ovp) the TPSM84209 incorporates an overvoltage transient protection (ovtp) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. the ovtp circuit includes an overvoltage comparator to compare the fb pin voltage and internal thresholds. when the fb pin voltage goes above 108% vref, the high-side mosfet is forced off. when the fb pin voltage falls below 104% vref, the high-side mosfet is enabled again. advance information
18 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.14 thermal performance the typical thermal performance of the TPSM84209 is shown in figure 28 . the thermal image shows the typical temperature rise of TPSM84209 is 27.2 c above ambient when operated at v in = 12 v, v out = 3.3 v, i out = 2 a, with no airflow (lfm = 0). t a = 25 c figure 28. thermal image 7.3.15 thermal shutdown the internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 165 c (typ). the device reinitiates the power-up sequence when the junction temperature drops below 155 c (typ). advance information
19 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 active mode when v in is above the uvlo threshold and the en pin voltage is above the en high threshold, the TPSM84209 operates in the active mode. normal continuous conduction mode (ccm) occurs when inductor peak current is above 0 a. in ccm, the TPSM84209 operates at a fixed frequency. 7.4.2 eco-mode operation the TPSM84209 device is designed to operate in high-efficiency, pulse-skipping mode under light load conditions. pulse skipping initiates when the switch current falls to 500 ma typically. during pulse skipping, the low-side fet turns off when the switch current falls to 0 a. the switching node (sw pin) waveform takes on the characteristics of discontinuous conduction mode (dcm) operation and the apparent switching frequency decreases. as the output current decreases, the perceived time between switching pulses increases. 7.4.3 shutdown mode the en pin provides electrical on and off control for the TPSM84209. when the en pin voltage is below the en threshold, the device is in shutdown mode. in shutdown mode the standby current is 2 a, typically. the TPSM84209 also employs uvlo protection. if v in is below the uvlo level, the output of the regulator turns off. advance information
20 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TPSM84209 is a synchronous, step-down dc-dc power module. it is used to convert a higher dc voltage to a lower dc voltage with a maximum output current of 2.5 a. the following design procedure can be used to select components for the TPSM84209. alternately, the webench ? software may be used to generate complete designs. when generating a design, the webench software utilizes an iterative design procedure and accesses comprehensive databases of components. see www.ti.com/webench for more details. 8.2 typical application the TPSM84209 requires only a few external components to convert from a wide input-voltage-supply range to a wide range of output voltages. figure 29 shows a basic TPSM84209 schematic with only the minimum required components. figure 29. TPSM84209 typical application 8.2.1 design requirements for this design example, use the parameters listed in table 5 and the following design procedures. table 5. design example parameters design parameter value input voltage v in 24 v typical output voltage v out 5 v output current rating 2 a 8.2.2 detailed design procedure 8.2.2.1 output voltage setpoint the output voltage of the TPSM84209 device is externally adjustable using a resistor divider (r fbt and r fbb ) between vout, fb, and gnd. with a fixed value of 10 k for r fbt , select the value of r fbb from table 1 or calculate using equation 2 : (2) for a output voltage of 5 v, the formula yields a value of 1.36 k . choose the closest available value of 1.37 k for r fbb . 6 r fbb = (k ) (v out 0.6) vin gnd v in = 24v vout v out = 5 v fb 10 k o en TPSM84209 10 f 50 v 1.37 k o 47 f 10 v 47 f 10 v advance information
21 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.2 input capacitors for this design, a 10- f, x7r dielectric ceramic capacitor rated for 50 v is used for the input decoupling capacitor. 8.2.2.3 output capacitors the minimum required output capacitance for a 5-v output is two 47- f ceramic capacitors. for this design, two 47- f, x5r dielectric ceramic capacitors rated for 16 v is used for the output capacitance. 8.2.2.4 enable control the en pin provides electrical on/off control of the device. if an application requires control of the en pin, use open-drain or open-collector output logic to interface with the pin. for this design, a small-signal, low-leakage mosfet (bss138) was used. 8.2.3 application waveforms figure 30. start-up waveforms v in = 24 v v out = 5 v i out = 2 a figure 31. output ripple and ph node waveforms 9 power supply recommendations the TPSM84209 is designed to operate from an input-voltage-supply range between 4.5 v and 28 v. this input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. the resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the TPSM84209 supply voltage that can cause a false uvlo fault triggering and system reset. if the input supply is located more than a few inches from the TPSM84209 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. typically, a 47- f or 100- f electrolytic capacitor is sufficient. advance information
22 TPSM84209 slvse31 ? january 2018 www.ti.com product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout the performance of any switching power supply depends as much upon the layout of the pcb as the component selection. see the following guidelines to design a pcb with the best power conversion performance, thermal performance, and minimized generation of unwanted emi. 10.1 layout guidelines to achieve optimal electrical and thermal performance, an optimized pcb layout is required. figure 32 and figure 33 , shows a typical pcb layout. some considerations for an optimized layout are: ? use large copper areas for power planes (vin, vout, and gnd) to minimize conduction loss and thermal stress. ? place ceramic input and output capacitors close to the device pins to minimize high frequency noise. ? locate additional output capacitors between the ceramic capacitor and the load. ? place the output voltage feedback resistors, r fbt and r fbb , as close as possible to their respective pins. ? use multiple vias to connect the power planes to internal layers. 10.2 layout examples figure 32. typical top-layer layout figure 33. typical gnd layer advance information
23 TPSM84209 www.ti.com slvse31 ? january 2018 product folder links: TPSM84209 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks eco-mode, e2e are trademarks of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 7-feb-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTPSM84209rkht active qfn rkh 9 250 tbd call ti call ti -40 to 85 TPSM84209rkht preview qfn rkh 9 250 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 7-feb-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTPSM84209rkht active qfn rkh 9 250 tbd call ti call ti -40 to 85 TPSM84209rkht preview qfn rkh 9 250 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
www.ti.com package outline c 4x 0.35 0.25 4x 0.6 0.4 2.1 max (0.2) typ 0.05 0.00 3x 0.45 0.35 2x 1.125 0.05 2x 2.25 0.05 3x 0.9 0.7 2x 1.9 pkg .0000 2x 1.05 2x 0.05 6x 0.65 2x 0.85 2x ( )0.625 b 4.1 3.9 a 4.6 4.4 (0.175) typ 2x ( 0.25) 2x (0.8) 8x (0.3) qfn - 2.1 mm max height rkh0009a plastic quad flatpack - no lead 4223793/b 09/2017 pin 1 index area 0.08 c seating plane 1 3 4 6 9 0.1 c a b 0.05 thermal pad 2x exposed 7 symm 0.1 c a b 0.05 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance. 0.08 c scale 2.500
www.ti.com example board layout .0000 2x ( )1.85 ( )1.7 2x ( )0.8 ( )1.16 ( )1.98 .000 pkg 0 2x ( )1.05 2x ( )2.1 ( )0.275 ( )1.77 2x ( )0.05 2x ( )0.625 ( )2.23 ( )1.95 2x ( )1.45 0.05 min typ ( )1.23 ( )0.23 ( )0.77 ( )0.52 ( )0.925 ( )1.33 ( )1.575 ( )1.7 2x ( )0.7 6x ( )1.825 4x (0.7) 4x (0.3) 3x (1) 3x (0.4) 2x (2.25) (0.375) typ (0.96) (4.6) 2x ( 0.35) keep out area 2x ( )0.85 2x ( )1.9 8x (0.3) 6x (0.65) (r0.05) typ qfn - 2.1 mm max height rkh0009a plastic quad flatpack - no lead 4223793/b 09/2017 notes: (continued) 4. this package is designed to be soldered to thermal pads on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. it is recommended that vias under paste be filled, plugged or tented. land pattern example solder mask defined scale:20x 1 3 4 6 7 9 symm metal under solder mask typ solder mask opening typ
www.ti.com example stencil design .0000 2x ( )1.85 2x ( )1.7 8x ( )2.0125 6x ( )1.165 .000 pkg 0 2x ( )1.9 2x ( )1.05 2x ( )0.05 2x ( )0.115 2x ( )0.925 ( )1.95 2x ( )1.735 4x (0.7) 4x (0.3) 6x (0.92) (r0.05) typ 3x (1) 3x (0.4) 8x (0.3) 8x (0.375) 2x ( )0.85 2x ( )2.1 6x) (0.65 6x (0.61) qfn - 2.1 mm max height rkh0009a plastic quad flatpack - no lead 4223793/b 09/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 6 symm exposed metal typ solder paste example based on 0.125 mm thick stencil printed solder coverage by area under package pads 3 & 4: 71% scale:25x 1 3 4 7 9 solder mask edge typ metal under solder mask typ
package option addendum www.ti.com 7-feb-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTPSM84209rkht active qfn rkh 9 250 tbd call ti call ti -40 to 85 TPSM84209rkht preview qfn rkh 9 250 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
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